Typical solid state memory devices (dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM)) employ micro-electronic circuit elements for each memory bit in memory applications. For typical non-volatile memory elements (like EEPROM, i.e., “flash” memory), floating gate field effect transistors are employed as the data storage device. These devices hold a charge on the gate of the field effect transistor to store each memory bit and have limited re-programmability. They are also slow to program.
During semiconductor and memory device manufacture, various layers of materials must be removed or reduced in order to form the various components of the circuits on the wafer, which typically is achieved by chemical-mechanical polishing (CMP). Many traditional CMP compositions are selective for removal of one type of integrated circuit component relative to another component.
Compositions and methods for CMP of the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries, CMP slurries, and CMP compositions) for CMP of surfaces of semiconductor substrates (e.g., for integrated circuit manufacture) typically contain an abrasive, various additive compounds, and the like.
In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate, urging the substrate against the polishing pad. The pad and carrier, with its attached substrate, are moved relative to one another. The relative movement of the pad and substrate serves to abrade the surface of the substrate to remove a portion of the material from the substrate surface, thereby polishing the substrate. The polishing of the substrate surface typically is further aided by the chemical activity of the polishing composition (e.g., by oxidizing agents, acids, bases, or other additives present in the CMP composition) and/or the mechanical activity of an abrasive suspended in the polishing composition. Typical abrasive materials include silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide.
Flash memory devices with 3-dimensional transistor stacking (3D flash memory) are increasingly popular. Polishing slurries for 3D flash applications generally should provide relatively high removal rates for silicon oxide (e.g., plasma-enhanced tetraethylorthosilicate-derived silicon dioxide, also known as “PETEOS” or “TEOS”), silicon nitride, and polysilicon, as well as good surface topography (e.g., dishing less than about 50 Å) and low defect levels (e.g., less than about 50 defects-per-wafer). Such a combination of features typically is not found in existing CMP compositions or methods. Consequently, there is an ongoing need to develop new polishing methods and compositions that provide such beneficial properties. The present invention addresses this ongoing need. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.